Electrostatic discharge (ESD) is a phenomenon where electrostatic charges migrate from a non-conductive surface via a conductive material. Since an electrostatic voltage is usually quite high, the ESD can easily damage the substrate and other components of an integrated circuit. For example, an electrostatic voltage from hundreds to thousands of volts can be created on a human body walking on a carpet under a higher relative humidity, while more than 10,000 volts can be created under a lower relative humidity. Also, an electrostatic voltage from hundreds to thousands of volts can be created in machines for packaging or testing integrated circuits. Therefore, when a human body or a machine carrying electrostatic charges contacts a chip, a large transient ESD current is generated, damaging or destroying the integrated circuits on the chip.
To protect the integrated circuits from being damaged by ESD, ESD devices capable of conducting an ESD current to ground are incorporated into the integrated circuits. Grounded gate NMOS (GGNMOS) devices are commonly used in protecting circuits.
A typical GGNMOS ESD protection circuit is illustrated in FIG. 1. The ESD protection circuit includes a GGNMOS 8 for protecting the circuit 6. The gate 14 and source 12 of the GGNMOS 8 are coupled to the power line VSS4, where VSS is typically grounded. Under normal operation, GGNMOS 8 is turned off so that it does not affect circuit 6. When an ESD transient occurs to the circuit 6, the GGNMOS 8 is turned on, and the ESD current is conducted to VSS4. In order to conduct a high ESD current, the GGNMOS 8 typically has a great device dimension, such as W/L=500/0.5 in a typical 0.35μ CMOS technology. With such a device dimension, the GGNMOS 8 typically has a multiple-finger poly gate. It has been found that a GGNMOS with a large layout area and a great device dimension may only sustain a low ESD current because all portions of the GGNMOS cannot be uniformly turned-on during the ESD stress. Only a portion of the large-dimension GGNMOS is turned on to bypass the ESD current, but most of the portions stay off during the ESD stress.
FIG. 2 illustrates a top view of a conventional GGNMOS. Only one finger is shown with a gate electrode 18, a drain region 14 and a source region 16. Contact plugs 261 through 267 connect to the drain region 14. A metal line 28 connects drain side contact plugs 261 through 267 to the circuit being protected. Contact plugs 221 through 227 connect to the source region 16. A metal line 24 couples contact plugs 221 through 227 to the p-well pick-up regions 20 and 21 that are located at the ends of the gate electrode 18. P-well pick-up regions 20 and 21 are typically grounded.
Multiple contact plugs divide the source region 14 and drain region 16 into sub regions. For simplicity purposes, each sub drain region and sub source region is referred to as the contact plug number next to it. The GGNMOS can be treated as sub NMOS transistors 321 through 327 connected in parallel. Each sub NMOS transistor 321 through 327 is formed of a drain 261 through 267, a gate electrode 18 and a source 221 through 227, respectively. When an ESD current occurs, it first flows from metal line 28 to contact plugs 261 through 267, then to the sub transistors 321 through 327 that are turned on. The ESD current then goes through contact plugs 221 through 227, then to metal 24, and finally to p-well pick-up regions 20 and 21. It is to be noted that besides the current flowing from the drain to the source of each transistor, there is also a substrate current flowing at a direction from sub transistor 324 to transistors 325, 326 and 327, and a substrate current flowing at a direction from sub transistor 324 to transistors 323, 322 and 321.
FIG. 3 illustrates a transmission-line model for the GGNMOS shown in FIG. 2. Each of the sub transistors 321 through 327 illustrated in FIG. 2 is modeled by an equivalent circuit 401 through 407. Circuits 401 through 407 are coupled in parallel. The equivalent circuit of the GGNMOS has an n-p-n structure, which is formed of drain(n)-substrate(p)-source(n). The resistors G1 through G7 are the substrate resistance of vertical path (from the top channel between the source 14 and drain 16 to the deep substrate, i.e., direction from gate to substrate or direction which penetrates into paper). Resistors Rsub1 through Rsub7 are the lateral substrate resistance from the deep substrate to the p-well pick-up regions. When an ESD current IESD occurs, it is distributed to circuits 401 through 407 and sunk to ground at node 4. As discussed in FIG. 2, the ESD current IESD also goes through substrate resistors Rsub3, Rsub2 and Rsub1 to ground at node 4. It is appreciated that sub transistor 324 has the highest substrate resistance since it is furthest from the ESD sink point 4. The substrate resistances induce a voltage drop on the substrate 2. Therefore, the sub transistor 324 is likely to be turned on earlier than any other transistor. Similar analysis reveals that transistors in the center are more likely to be turned on earlier than transistors at the ends.
Turning on sub transistors at different times causes current crowding. At a lower ESD current, only sub transistors in the center, such as transistors 324, 323 and 325 are turned on. When current increases, from the center to the end, more and more sub transistors are turned on until at a certain time all sub transistors are turned on. It is noted that even when all the sub transistors are on, the center transistors carry more ESD current than the transistors at the ends so that they are more prone to damage.
In order to improve the ESD level of such a large dimension GGNMOS, the multiple fingers of the large dimension GGNMOS have to be uniformly triggered on to share ESD current. If all the fingers and the sub transistors of the large dimension GGNMOS can be uniformly turned on during the ESD stress condition, the GGNMOS can sustain a much higher ESD level. Therefore, there is the need to achieve uniformity among the multiple sub transistors of the large-dimension GGNMOS.